(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a sub-quarter-micron MOSFET structure in the fabrication of integrated circuits.
(2) Description of the Prior Art
In sub-quarter-micron MOSFET architecture, it is necessary to use ultra-shallow source/drain regions. Low energy ion implantation is typically used for the formation of such regions. However, problems occur with these devices. So-called "Gerhard Hobler effects," caused by lateral doping variations are an issue for these devices.
For example, FIG. 1 illustrates a semiconductor substrate 10, preferably composed of monocrystalline silicon. A layer of silicon oxide 12 is formed on the surface of the substrate. A polysilicon layer is deposited and patterned to form gate electrode 16. A typical LDD (lightly doped source and drain) structure is formed by an LDD mask implant followed by spacer oxide deposition and etching and then a source/drain mask implant. Lightly doped source and drain regions 20 are shown in FIG. 1.
FIG. 1 illustrates "hot spots" 23 in the lightly doped source/drain regions which cause current leakage. These "hot spots" are formed as a result of the interaction of relatively low energy ions with the sidewall of the gate.
Source/drain lateral misalignment with the gate, seen at 25 where there is a gap between the source/drain region 20 and the gate edge, is the origin for the device subthreshold characteristics variations. The conditions for the conducting channel onset for the gap 25 region are different from those for the under-the-gate regions. Therefore, not only subthreshold, but also threshold characteristics would depend on the gap width. These variations also cause enhanced hot carrier injection and gate degradation resulting in a decrease in the reliability level of the device.
Micro-trenches, such as 27, may occur during gate etching. These micro-trenches cause nucleation of crystal defects and thus, excessive leakage currents. They also cause a doping profile non-uniformity and hence an increase in standby currents of the transistor and threshold characteristics variation, such as in saturation current.
Gate critical dimension (CD) reproducibility has been a concern of all of the sub-micron technologies. Minimum gate length corresponds to the minimum feature size of any technology generation; that is, the edge of a lithography tool capability. Therefore, considerable relative variations of a gate CD are inevitable. At the same time, device characteristics strongly depend on the gate length.
U.S. Pat. No. 5,538,913 to Hong teaches forming a gate electrode in a trench wherein conducting spacers form part of the gate. U.S. Pat. No. 5,270,257 to Shin teaches forming a gate electrode in a trench and growing an epitaxial N+ layer over an implanted N- layer. U.S. Pat. No. 5,464,780 to Yamazaki discloses the fabrication of gate electrodes at the side surfaces of a trench in the fabrication of a memory cell. U.S. Pat. No. 5,108,937 to Tsai et al teaches removing a field oxide region and forming a gate electrode in the depression left by the field oxide region. U.S. Pat. No. 5,623,153 to Liang et al shows the formation of a gate electrode and formation of N- and N+ regions by outdiffusion from doped pad oxide and doped polysilicon layers, respectively.